1. Field of the Invention
The present invention relates to a PLL (phase-locked loop) frequency synthesizer and, more particularly, to a fractional-N frequency synthesizer comprising a frequency synthesizer whose frequency divide ratio is variable.
2. Description of the Related Art
A conventional fractional-N frequency synthesizer using a PLL is described, for example, in Japanese patent laid-open No. 154935/1998 (counterpart of U.S. Pat. No. 5,818,303). This fractional-N frequency synthesizer described in this laid-open publication is shown in FIG. 7, where the conventional fractional-N frequency synthesizer is indicated by 70 and has a voltage-controlled oscillator (VCO) 76 producing an output signal of frequency fo. A part of this output signal of frequency fo is fed to a variable frequency divider 77. The frequency divider 77 and an accumulator 78 frequency-divide the signal of frequency fo by an integer N or (N+1) varying periodically, thus producing a compared signal fp. The phase difference between a reference signal frequency fr and the compared signal fp is detected by a phase comparator 72, which applies a voltage pulse having a pulse width corresponding to the phase difference to a charge pump circuit 73. This charge pump circuit 73 produces an output current Icp, which is smoothed by a loop filter 75 and converted into a voltage. This voltage is used as a control voltage for the voltage-controlled oscillator 76. Owing to this configuration, the average frequency fo of the output signal from the voltage-controlled oscillator 76 can be controlled to
fo=fr[N+(F/2n)]
where F is a value applied to the accumulator every phase comparison period (period of fr or fp) and n is an integer determined by the n-bit register structure of the accumulator. Therefore, the average frequency fo of the output signal can be switched in a frequency width smaller than the frequency fr of the reference signal by switching F as well as N.
Under this condition, however, the frequency fo of the actual output signal constantly varies periodically, producing spurious signals off the center frequency. That is, in this conventional fractional-N frequency synthesizer 70, the input value F is applied to and accumulated in the accumulator 78 of the n-bit structure every phase comparison period (period of fr or fp). The output is switched from 0 to 1 by an overflow signal Sov produced when the accumulator 78 overflows. The frequency divide ratio of the frequency divider 77 is switched from N to (N+1). Because of this structure, the frequency fo of the output signal is switched between fo1=(N+1) fr and fo2=Nfr periodically, i.e., every (2n/F) phase comparison periods. As a result, the above-described spurious signals are produced. Therefore, this conventional fractional-N frequency synthesizer 70 further includes a spurious-canceling circuit 79 to cancel out undesired spurious signals. This spurious-canceling circuit 79 produces a pulse voltage signal having a pulse width proportional to the output value of the accumulator since a timing when a reset signal is inputted to it. Another circuit is included which is driven by the pulse voltage signal and produces a spurious canceling-circuit output current Isc. This spurious-canceling current Isc and the output current Icp from the charge pump circuit 73 are added up to produce an electrical current that is smoothed by the loop filter 75 and converted into a voltage. This voltage is used as a control voltage for the voltage-controlled oscillator 76. In this way, spurious signals produced due to periodical switching of the frequency divide ratio of the variable frequency divider 77 between N and (N+1) are canceled out.
However, spurious signals from the conventional fractional-N frequency synthesizer 70 shown in FIG. 7 are essentially produced by the structure in which the frequency divide ratio of the variable frequency divider 77 is periodically switched between N and (N+1) by the accumulator 78 of n-bit register structure. As a result, a spectrum of periodically conspicuous intensity occurs. For example, in FIG. 3, as shown in a spectrum 31, in a simulation where no spurious cancellation is performed under conditions of a reference frequency fr=1 MHz and a frequency divide ratio of 315(N)+{fraction (15/16)}, the output signal from the conventional fractional-N frequency synthesizer 70 produces a spurious signal 32 of level of xe2x88x9210 dB at maximum. As a result, the conventional fractional-N frequency synthesizer 70 has the problem that spurious signal cannot be reliably canceled unless the accuracy of the spurious-canceling circuit is increased. For example, where the spurious cancellation accuracy error is set to 5%, for example, using the same simulation as in FIG. 3, the maximum spectrum of spurious signals 42 produced by the conventional fractional-N frequency synthesizer 70 is about xe2x88x9236 dB, as in a spectrum 41 shown in FIG. 4. That is, practical results are not produced. Consequently, the conventional fractional-N frequency synthesizer 70 needs an accurate spurious-canceling circuit. Hence, the circuit is made expensive.
It is an object of the present invention to provide a fractional-N frequency synthesizer free of the foregoing problems and a method of operating the synthesizer.
This object is achieved by a method of operating a fractional-N frequency synthesizer in accordance with the present invention, the method starting with preparing a sigma-delta noise shaper. The integral and fractional parts of a frequency divide ratio-setting value for frequency-dividing the output signal are set. The fractional part of the frequency divide ratio-setting value is applied to the sigma-delta noise shaper every phase comparison period. The output from the sigma-noise shaper and the integral part of the frequency divide ratio-setting value are summed up. Using the resulting sum as a frequency divide ratio, the output signal is frequency-divided. The difference between the fractional part of the frequency divide ratio-setting value and the output from the sigma-delta noise shaper is produced. This difference is accumulated in the accumulator every phase comparison period. A spurious-canceling value is produced based on the accumulator""s value.
In this method according to the invention, where a general third-order sigma-delta noise shaper is used as the above-described sigma-delta noise shaper, for example, a transfer function indicating the relation between the quantized output Y from the third-order sigma-delta noise shaper and input X is given by Y=X+(1xe2x88x92zxe2x88x921)3Nq, where zxe2x88x921 indicates one sampling delay and Nq indicates quantization noise. The quantization noise Nq is almost random in nature, i.e., white noise. Accordingly, if number F indicating the fractional part of the frequency divide ratio-setting value is applied to the third-order noise shaper every phase comparison period, a random integer sequence S whose average value is equal to the fractional part F of the frequency divide ratio-setting value is produced every phase comparison period. That is, almost random integer sequence S whose average value is F is produced, the sequence S being from xe2x88x923 to +4.
The output from this sigma-delta noise shaper and the integral part N of the frequency divide ratio-setting value are summed up. A sequence of almost random integers is produced. The average value of this sequence is equal to N+F. The sequence is from Nxe2x88x923 to N+4. This random sequence is used as a frequency divide ratio in the fractional-N frequency synthesizer. An output signal fo having a frequency that is (N+F) times as high as the reference frequency fr on average is produced. Therefore, in the sigma-delta noise shaper of the present invention, the frequency divide ratio does not vary periodically, unlike the conventional method of operating a fractional-N frequency synthesizer, because an almost random integer sequence S whose average value is equal to F is produced, the sequence S being from xe2x88x923 to +4, for example. For this reason, generation of spurious signals having periodically conspicuous spectral intensities as encountered with the prior art technique is avoided.
In this way, in the fractional-N frequency synthesizer according to the present invention, spurious signals having periodically conspicuous spectral intensities are not produced. With respect to randomly generated spurious signals, the difference between the fractional part of the frequency divide ratio-setting value and the output from the sigma-delta noise shaper is created. This difference is accumulated in the accumulator every phase comparison period. A spurious-canceling value is produced based on the value of the accumulator. Thus, spurious suppression is performed.
In the fractional-N frequency synthesizer according to the present invention, spurious signals of periodically conspicuous spectral intensities are not produced. Therefore, produced spurious signals can be canceled up to a practical level even if the spurious-canceling circuit is not accurate.
A method as set forth in claim 2 of the invention is based on the method described above and further characterized in that there are further steps of converting the output from the accumulator into an analog value and adding the analog value to the output from a phase comparator that produces the phase difference between an output signal and a reference signal, the output signal being frequency-divided by the frequency divide ratio.
In the method according to the invention including these steps, a value indicative of the difference between the fractional part of the frequency divide ratio-setting value and the output from the sigma-delta noise shaper corresponds to the error between the frequency divide ratio and the frequency divide ratio-setting value every phase comparison period. This error is accumulated in the accumulator. The output from the accumulator is converted into an analog value. This analog value is added to the output from the phase comparator as a spurious-canceling value. Thus, the error in the frequency divide ratio is compensated. As a consequence, produced spurious signals are canceled.
A method as set forth in claim 3 of the invention is based on the method as set forth in claim 2 and further characterized in that timing at which the output from the accumulator that is analog converted using the period of the output signal is produced is limited to a range close to the output timing of the phase comparator.
In the method according to the invention having the features described above, the timing at which the spurious-canceling value is added is limited to the range closest to the output of the phase comparator, utilizing the period of the output signal frequency. This prevents deviation between the output timing of the phase comparator and the output timing of the spurious-canceling circuit so that spurious signals being caused by such the deviation are suppressed.
Claim 4 of the present invention provides a fractional-N frequency synthesizer having a voltage-controlled oscillator, a phase comparator, and a variable frequency divider mounted between the voltage-controlled oscillator and the phase comparator. This frequency synthesizer comprises: means for setting the integral and fractional parts of a frequency divide ratio-setting value for frequency-dividing the output signal from the voltage-controlled oscillator by the variable frequency divider; a sigma-delta noise shaper to which the fractional part of the frequency divide ratio-setting value is applied every phase comparison period; and adder means for summing up the output from the sigma-delta noise shaper and the integral part of the frequency divide ratio-setting value to thereby produce a sum. The output from the adder means is used as a frequency divide ratio by the variable frequency divider, which in turn frequency-divides the output signal from the voltage-controlled oscillator. The frequency-divided output signal is supplied to the phase comparator.
In the fractional-N frequency synthesizer of this structure, the sigma-delta noise shaper randomly produces a frequency divide ratio which is an integer and whose average value is equal to the frequency divide ratio-setting value. This frequency divide ratio is fed to the variable frequency divider. Therefore, spurious signals of periodically conspicuous spectral intensities are not essentially produced, unlike the conventional fractional-N frequency synthesizer. Consequently, produced spurious signals can be canceled up to a practical level even if the spurious-canceling circuit is not accurate. Hence, a fractional-N frequency synthesizer can be constructed relatively economically.
Claim 5 of the invention provides a fractional-N frequency synthesizer which is based on the fractional-N frequency synthesizer as set forth in claim 4 and further characterized in that it further includes: means for creating the difference between the fractional part of the frequency divide ratio-setting value and the output from the sigma-delta noise shaper; means for accumulating the difference every phase comparison period; and means for producing a spurious-canceling value based on the accumulated value.
The fractional-N frequency synthesizer of this structure contains the spurious-canceling circuit of relatively simple construction as described above. Therefore, produced spurious signals can be effectively canceled. That is, in the present invention, spurious signals of periodically conspicuous spectral intensities are not produced essentially. In consequence, produced spurious signals can be canceled up to a practical level even with a spurious-canceling circuit of a simple structure.
Claim 6 of the invention provides a fractional-N frequency synthesizer which is based on the fractional-N frequency synthesizer as set forth in claim 5 and further characterized in that the means of the spurious-canceling circuit for producing the spurious-canceling value further includes means for limiting a timing to produce spurious-canceling value to a range close to the output timing of the phase comparator based on the period of the output signal from the voltage-controlled oscillator and adder means for adding the produced spurious-canceling value to the output from the phase comparator.
In the fractional-N frequency synthesizer of this structure, the output timing of the phase comparator and the timing at which the spurious-canceling value is added are restricted to a very close range by utilizing the period of the output signal frequency. This prevents deviation between the output timing of the phase comparator and the output timing of the canceling circuit so that spurious signals being caused by such the deviation are suppressed.
Claim 7 of the invention provides a fractional-N frequency synthesizer which is based on the fractional-N frequency synthesizer as set forth in claim 4 and further characterized in that there are further provided a random number generator and adder means for adding up the output from the random number generator and the output from the means for setting the fractional part of the frequency divide ratio-setting value. The output from the adder means is applied to the delta-sigma noise shaper.
In the fractional-N frequency synthesizer of this structure, the randomness of the output from the sigma-delta noise shaper is enhanced further. Generation of spurious signals having periodically conspicuous spectral intensities is suppressed further.